Continuing improvements in semiconductor processing techniques employed for the layout and fabrication of integrated circuits have resulted in a substantial increase in the density and complexity of building blocks (both custom and non-application specific components) available to the analog and mixed (digital/analog) signal processing system designer. Indeed, chip architectures may employ hundreds of thousands of circuits to implement a prescribed signal processing function.
Now although semiconductor manufacturing processing parameters allow the interconnect material (metal, contacts, vias), through which signal and circuit element bias paths are provided among respective components of a given architecture, to be fabricated with extremely narrow line widths and thereby ostensibly realize a very compact circuit layout, performance factors and not merely density, per se, must be taken into consideration before a given design may be `reduced to silicon`.
A significant influence in mean time to failure (MTF), or over what length of time a circuit will satisfactorily perform its intended signal processing function is an undesirable, but unavoidable, effect called electromigration, which causes the original physical characteristics of a given interconnect topography to be altered in the course of operation of the circuit due to current flow through metal, vias and contacts. Specifically, electromigration is a physical phenomenon whereby, during circuit operation, metal atoms are pushed by the conducting electrons in the direction of current flow. Any divergence in the directed mass flux causes physical discontinuities in the metal that eventually leads to failure of the circuit.
Electromigration typically manifests itself in the form of hillocks, whiskers and voids in the metallic conductive material. Because electromigration is a natural consequence of current flow through metal over time, it must be taken into account as a priority consideration before a given circuit design is fabricated; in fact, MTF for electromigration can be predicted as a function of current density and temperature.
Using well developed electromigration models (respectively associated with metallic line, contact and via material), which limit the width of interconnect as a function of maximum current flow and temperature, circuit designers usually invest a significant amount of time identifying and verifying those portions of a circuit architecture that must have a dimension (line width) that is greater than a deterministically prescribed minimum width. Because this process is labor intensive it is error prone and is often not invoked until the end of the product development cycle, which undesirably delays completion of the circuit layout.